#ifndef INCLUDED_CYFITTERKEIL_INC
#define INCLUDED_CYFITTERKEIL_INC
$INCLUDE (cydevicekeil.inc)
$INCLUDE (cydevicekeil_trm.inc)

; Counter_1_CounterUDB
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
Counter_1_CounterUDB_sC8_counterdp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
Counter_1_CounterUDB_sC8_counterdp_u0__A0_REG EQU CYREG_B0_UDB05_A0
Counter_1_CounterUDB_sC8_counterdp_u0__A1_REG EQU CYREG_B0_UDB05_A1
Counter_1_CounterUDB_sC8_counterdp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
Counter_1_CounterUDB_sC8_counterdp_u0__D0_REG EQU CYREG_B0_UDB05_D0
Counter_1_CounterUDB_sC8_counterdp_u0__D1_REG EQU CYREG_B0_UDB05_D1
Counter_1_CounterUDB_sC8_counterdp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
Counter_1_CounterUDB_sC8_counterdp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
Counter_1_CounterUDB_sC8_counterdp_u0__F0_REG EQU CYREG_B0_UDB05_F0
Counter_1_CounterUDB_sC8_counterdp_u0__F1_REG EQU CYREG_B0_UDB05_F1
Counter_1_CounterUDB_sC8_counterdp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sC8_counterdp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK EQU 0x80
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS EQU 7
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG EQU CYREG_B0_UDB05_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__MASK EQU 0x80
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__0__MASK EQU 0x01
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__0__POS EQU 0
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__1__MASK EQU 0x02
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__1__POS EQU 1
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__3__MASK EQU 0x08
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__3__POS EQU 3
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__5__MASK EQU 0x20
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__5__POS EQU 5
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__6__MASK EQU 0x40
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__6__POS EQU 6
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK EQU 0x6B
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK_REG EQU CYREG_B0_UDB05_MSK
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_REG EQU CYREG_B0_UDB05_ST

; CharLCD_1_LCDPort
CharLCD_1_LCDPort__0__MASK EQU 0x01
CharLCD_1_LCDPort__0__PC EQU CYREG_PRT2_PC0
CharLCD_1_LCDPort__0__PORT EQU 2
CharLCD_1_LCDPort__0__SHIFT EQU 0
CharLCD_1_LCDPort__1__MASK EQU 0x02
CharLCD_1_LCDPort__1__PC EQU CYREG_PRT2_PC1
CharLCD_1_LCDPort__1__PORT EQU 2
CharLCD_1_LCDPort__1__SHIFT EQU 1
CharLCD_1_LCDPort__2__MASK EQU 0x04
CharLCD_1_LCDPort__2__PC EQU CYREG_PRT2_PC2
CharLCD_1_LCDPort__2__PORT EQU 2
CharLCD_1_LCDPort__2__SHIFT EQU 2
CharLCD_1_LCDPort__3__MASK EQU 0x08
CharLCD_1_LCDPort__3__PC EQU CYREG_PRT2_PC3
CharLCD_1_LCDPort__3__PORT EQU 2
CharLCD_1_LCDPort__3__SHIFT EQU 3
CharLCD_1_LCDPort__4__MASK EQU 0x10
CharLCD_1_LCDPort__4__PC EQU CYREG_PRT2_PC4
CharLCD_1_LCDPort__4__PORT EQU 2
CharLCD_1_LCDPort__4__SHIFT EQU 4
CharLCD_1_LCDPort__5__MASK EQU 0x20
CharLCD_1_LCDPort__5__PC EQU CYREG_PRT2_PC5
CharLCD_1_LCDPort__5__PORT EQU 2
CharLCD_1_LCDPort__5__SHIFT EQU 5
CharLCD_1_LCDPort__6__MASK EQU 0x40
CharLCD_1_LCDPort__6__PC EQU CYREG_PRT2_PC6
CharLCD_1_LCDPort__6__PORT EQU 2
CharLCD_1_LCDPort__6__SHIFT EQU 6
CharLCD_1_LCDPort__AG EQU CYREG_PRT2_AG
CharLCD_1_LCDPort__AMUX EQU CYREG_PRT2_AMUX
CharLCD_1_LCDPort__BIE EQU CYREG_PRT2_BIE
CharLCD_1_LCDPort__BIT_MASK EQU CYREG_PRT2_BIT_MASK
CharLCD_1_LCDPort__BYP EQU CYREG_PRT2_BYP
CharLCD_1_LCDPort__CTL EQU CYREG_PRT2_CTL
CharLCD_1_LCDPort__DM0 EQU CYREG_PRT2_DM0
CharLCD_1_LCDPort__DM1 EQU CYREG_PRT2_DM1
CharLCD_1_LCDPort__DM2 EQU CYREG_PRT2_DM2
CharLCD_1_LCDPort__DR EQU CYREG_PRT2_DR
CharLCD_1_LCDPort__INP_DIS EQU CYREG_PRT2_INP_DIS
CharLCD_1_LCDPort__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
CharLCD_1_LCDPort__LCD_EN EQU CYREG_PRT2_LCD_EN
CharLCD_1_LCDPort__MASK EQU 0x7F
CharLCD_1_LCDPort__PORT EQU 2
CharLCD_1_LCDPort__PRT EQU CYREG_PRT2_PRT
CharLCD_1_LCDPort__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
CharLCD_1_LCDPort__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
CharLCD_1_LCDPort__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
CharLCD_1_LCDPort__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
CharLCD_1_LCDPort__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
CharLCD_1_LCDPort__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
CharLCD_1_LCDPort__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
CharLCD_1_LCDPort__PS EQU CYREG_PRT2_PS
CharLCD_1_LCDPort__SHIFT EQU 0
CharLCD_1_LCDPort__SLW EQU CYREG_PRT2_SLW

; CounterISR
CounterISR__ES2_PATCH EQU 0
CounterISR__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN0
CounterISR__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD0
CounterISR__INTC_MASK EQU 0x01
CounterISR__INTC_NUMBER EQU 0
CounterISR__INTC_PRIOR_NUM EQU 7
CounterISR__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR0
CounterISR__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN0
CounterISR__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD0
CounterISR__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x00)

; clock_1
clock_1__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
clock_1__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
clock_1__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
clock_1__CFG2_SRC_SEL_MASK EQU 0x07
clock_1__INDEX EQU 0x00
clock_1__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
clock_1__PM_ACT_MSK EQU 0x01
clock_1__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
clock_1__PM_STBY_MSK EQU 0x01

; P0_4
P0_4__0__MASK EQU 0x10
P0_4__0__PC EQU CYREG_PRT0_PC4
P0_4__0__PORT EQU 0
P0_4__0__SHIFT EQU 4
P0_4__AG EQU CYREG_PRT0_AG
P0_4__AMUX EQU CYREG_PRT0_AMUX
P0_4__BIE EQU CYREG_PRT0_BIE
P0_4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
P0_4__BYP EQU CYREG_PRT0_BYP
P0_4__CTL EQU CYREG_PRT0_CTL
P0_4__DM0 EQU CYREG_PRT0_DM0
P0_4__DM1 EQU CYREG_PRT0_DM1
P0_4__DM2 EQU CYREG_PRT0_DM2
P0_4__DR EQU CYREG_PRT0_DR
P0_4__INP_DIS EQU CYREG_PRT0_INP_DIS
P0_4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
P0_4__LCD_EN EQU CYREG_PRT0_LCD_EN
P0_4__MASK EQU 0x10
P0_4__PORT EQU 0
P0_4__PRT EQU CYREG_PRT0_PRT
P0_4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
P0_4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
P0_4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
P0_4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
P0_4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
P0_4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
P0_4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
P0_4__PS EQU CYREG_PRT0_PS
P0_4__SHIFT EQU 4
P0_4__SLW EQU CYREG_PRT0_SLW

; P0_5
P0_5__0__MASK EQU 0x20
P0_5__0__PC EQU CYREG_PRT0_PC5
P0_5__0__PORT EQU 0
P0_5__0__SHIFT EQU 5
P0_5__AG EQU CYREG_PRT0_AG
P0_5__AMUX EQU CYREG_PRT0_AMUX
P0_5__BIE EQU CYREG_PRT0_BIE
P0_5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
P0_5__BYP EQU CYREG_PRT0_BYP
P0_5__CTL EQU CYREG_PRT0_CTL
P0_5__DM0 EQU CYREG_PRT0_DM0
P0_5__DM1 EQU CYREG_PRT0_DM1
P0_5__DM2 EQU CYREG_PRT0_DM2
P0_5__DR EQU CYREG_PRT0_DR
P0_5__INP_DIS EQU CYREG_PRT0_INP_DIS
P0_5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
P0_5__LCD_EN EQU CYREG_PRT0_LCD_EN
P0_5__MASK EQU 0x20
P0_5__PORT EQU 0
P0_5__PRT EQU CYREG_PRT0_PRT
P0_5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
P0_5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
P0_5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
P0_5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
P0_5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
P0_5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
P0_5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
P0_5__PS EQU CYREG_PRT0_PS
P0_5__SHIFT EQU 5
P0_5__SLW EQU CYREG_PRT0_SLW

; Miscellaneous
; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_LEOPARD
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_PANTHER EQU 3
CYDEV_CHIP_DIE_PSOC4A EQU 2
CYDEV_CHIP_DIE_PSOC5LP EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC3
CYDEV_CHIP_JTAG_ID EQU 0x1E028069
CYDEV_CHIP_MEMBER_4A EQU 2
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 4
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_3A
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_3A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_LEOPARD_PRODUCTION
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CONFIGURATION_CLEAR_SRAM EQU 1
CYDEV_CONFIGURATION_COMPRESSED EQU 0
CYDEV_CONFIGURATION_DMA EQU 1
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_DMA
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DEBUG_ENABLE_MASK EQU 0x01
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_INSTRUCT_CACHE_ENABLED EQU 0
CYDEV_INTR_RISING EQU 0x00000001
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA LIT '5.0'
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD LIT '5.0'
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0 LIT '5.0'
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1 LIT '5.0'
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2 LIT '5.0'
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3 LIT '5.0'
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERKEIL_INC */
